iES-12 – integrated Ethernet Switch

iES-12 integrated Ethernet Switch

The iES-12 integrated Ethernet Switch, is a rugged 12 port layer 2/3 managed gigabit Ethernet switch with end node timing and discrete signal capabilities for demanding test instrumentation environments on airborne, shipboard or mobile ground vehicles.

Switch traffic filtering capabilities include; Port User Limit Control, VLAN/ MAC Address (Static MAC Table), Packet/Bit Rate Limiters, Port Based and Frame Type and IP Filtering (ACL, Static/Dynamic Multicast). Audio Video Bridging (AVB) capability is also supported.

A programmable FPGA tied directly into the switch with two 1G interfaces provides line-rate packet processing capabilities. The FPGA also provides built-in IRIG 106 Chapter 7 PCM encoding & decoding. This allows PCM output of VLAN, mirrored or filtered Ethernet switch traffic or from the PCM input decoded Ethernet back out the switch Ethernet ports. Discrete outputs (programmable or data driven) can be used to control end node devices, on or off the network, as well as feedback into the iES-12 from discrete inputs.

With multiple time sources and outputs, the iES-12 provides end node device IRIG time signals. iES-12 contains a high time accuracy internal GPS receiver & a hardware based IEEE-1588v2 time engine both able to drive the internal IRIG-A/B/G Time Code Generator for time outputs. The IEEE-1588v2 time engine provides 1-4 independent clocks (ordinary, boundary, transparent, 1/2 step, peer-to-peer or end-to-end).

Features

● 12 Tri-Speed Ports with Layer 2/3 Management

● Connected FPGA for Data Processing

● CH7 PCM Encoder/Decoder

● Audio Video Bridging (AVB) Capability

● GPS Receiver w/ IRIG DC/AM/1PPS Outputs

● 1588v2 Clocks w/ Grand Master Capability

● 12 Tri-Speed Ports with Layer 2/3 Management

● Connected FPGA for Data Processing

● CH7 PCM Encoder/Decoder

● Audio Video Bridging (AVB) Capability

● GPS Receiver w/ IRIG DC/AM/1PPS Outputs

● 1588v2 Clocks w/ Grand Master Capability

Diagram

Features & Specifications

• Non-Blocking Wire Speed Performance for All Frame Sizes Up to 9.6KB
• FPGA for data processing, filtering & HDLC/CH7 PCM input/output
• 4K VLAN’s, 256 Filtering Policies
• 8K L2 Multicast Groups Addresses
• Port Mirroring & Link Aggregation
• CLI, Web GUI or SNMP Control & Monitoring
• RS-232 COM Port

Layer 2/3 Managed Switch

Layer 2/3 Managed Switch
12 10/100/1000 Speed Ports (Standard)
8K MAC Address
4K VLAN’s (IEEE 802.1Q)
VLAN Q-in-Q (IEEE 802.1ad) (Carrier Ethernet)
8K L2 Multicast Group Addresses
8K IPv4/IPv6 Multicast Groups
MLDv1 & MLDv2 w/ Source Forwarding
8 Priorities & 8 QoS Queues per Port
Jumbo Frames up to 9.6KB
Programmable MTU Per Port
Port Mirroring & Link Aggregation (IEEE 802.3ad)
Rapid Spanning Tree Protocol (IEEE 802.1w)
Multiple Spanning Tree Protocol (IEEE 802.1s)
Full-Duplex Flow Control (IEEE 802.3X)
Packet Filtering Engine w/ up to 256 Entries
Port Ingress Policing w/ Flow Control
Flood Controllers (Broadcast/Multicast/Unicast)
Port/MAC-Based Access Control (IEEE 802.1X)

PCM - CH7/HDLC Encoder/Decoder

1 RS-422 PCM Input, 2Mb to 20Mb and 1 RS-422 PCM Output, 2Mb to 20Mb
CH7/HDLC PCM Encoder/Decoder
Chapter 10 published stream

The standard PCM input/output format is ISO 13239 HDLC or IRIG 106-15 Chapter 7 Telemetry Downlink Standard from internal switch port Ethernet traffic. The switch port may contain an IRIG 106 Chapter 10 published stream, filtered or mirrored port switch traffic from a network.